Using the NS-2 network simulator for evaluating network on chips (NoC)

Muhammad Ali; Michael Welzl; Awais Adnan; Farrukh Nadeem; IEEE

doi:10.1109/ICET.2006.335967

Back

Conference proceeding

Using the NS-2 network simulator for evaluating network on chips (NoC)

Muhammad Ali, Michael Welzl, Awais Adnan, Farrukh Nadeem and IEEE

SECOND INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES 2006, PROCEEDINGS, pp.506-512

01/01/2006

DOI: https://doi.org/10.1109/ICET.2006.335967

Abstract

Computer Science

Computer Science, Artificial Intelligence

Computer Science, Theory & Methods

Imaging Science & Photographic Technology

Science & Technology

Technology

Telecommunications

Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs

Metrics

1 Record Views

Details

Title: Using the NS-2 network simulator for evaluating network on chips (NoC)
Creators - without role: Muhammad Ali - Universität Innsbruck
Michael Welzl - Universität Innsbruck
Awais Adnan
Farrukh Nadeem
IEEE
Publication Details: SECOND INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES 2006, PROCEEDINGS, pp.506-512
Publisher: IEEE
Number of pages: 7
Identifiers: 9940119808331
Academic Unit: King Abdulaziz University
Language: English
Resource Type: Conference proceeding