Abstract
VHDL is a hardware language used for describing (model) the digital systems that support both structural and behavior description. VHDL would enable us to evaluate or simulate several structural realizations of the same behavioral description. The paper presents the VHDL supports such as: modeling of digital systems that supports both structural and behavioral descriptions, modeling of combinational and sequential digital circuits, test modeling (testbench), modeling of the propagation delay and modeling of logic primitives. The paper introduce the VHDL codes for the previous modeling schemes