Abstract
Conference Title: 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD) Conference Start Date: 2018, March 19 Conference End Date: 2018, March 22 Conference Location: Yassmine Hammamet, Tunisia This paper proposes an FPGA-based implementation of a speed and memory efficient corners' detection Zynq FPGA based implementation for high frames resolution video processing systems. The proposed approach includes an original architecture supporting Harris & Stephen corner detector, a robust strategy for memory on a chip management to enhance data transmission and processing speed. The optimization of the whole processing is based on proposed HW /SW partition heuristics which allow to achieve different performances. The proposed implementation of the whole processing on Xilinx Zynq SoC FPGA is presented and the obtained temporal and quality performance are provided.