Abstract
3D integrated circuits introduce both advantages and disadvantages for security. Among the disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between two legitimate dies. Such a die could be used to snoop information traveling between dies, alter the data, or otherwise interfere with stack operation. In this article, we explore the use of in-stack circuitry and various testing procedures to detect an extra die through delay analysis even in the presence of process variations. Then, we explore the performance of these techniques when the attacker modifies some of the TSVs' characteristics to avoid detection. Our simulation results show that the proposed techniques can detect the Trojan die in a 3D stack, especially when the test structure that incorporates multiple TSVs between two dies is used.