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4.2 Gbit/s single-chip FPGA implementation of AES algorithm
Journal article   Peer reviewed

4.2 Gbit/s single-chip FPGA implementation of AES algorithm

F Rodriguez-Henriquez, N A Saqib and A Diaz-Perez
Electronics letters, Vol.39(15), pp.1115-1116
24/07/2003
DOI: https://doi.org/10.1049/el:20030746

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A high performance encryptor/decryptor core of the advanced encryption standard (AES) is presented. The proposed architecture is implemented on a single-chip FPGA using a fully pipelined approach. The results obtained show that this design offers up to 25.06% less area and yields up to 27.23% higher throughput than the fastest AES FPGA implementations reported to date.

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