Abstract
This paper presents a design exploration of a new EEG-based embedded system for home devices control. Two main issues are addressed in this work: the first one consists of an adaptive filter design to increase the classification accuracy for motor imagery. The second issue deals with the design of an efficient hardware/software embedded architeclture integrating the entire EEG signal processing chain. In this embedded system organization, the pre-processing techniques, which are time consuming, are integrated as hardware accelerators. The remaining blocks (Intellectual Properties - IP) are developed as embedded-software running on an embedded soft-core processor. The pre-processing step is designed to be self-adjusted according to the intrinsic characteristics of each subject. The feature extraction process uses the Common Spatial Pattern (CSP) as a filter due to its effectiveness to extract the ERD/ERS (Event-Related Desynchronization/Synchronization) effect, where the classifier is based on the Mahalanobis distance. The advantage of the proposed system lies in its simplicity and short processing time while maintaining a high performance in term of classification accuracy. A prototype of the embedded system has been implemented on an Altera FPGA-based platform (Stratix-IV). It is shown that the proposed architecture can effectively extract discriminative features for motor imagery with a maximum frequency of 150 MHz. The proposed system was validated on EEG data of twelve subjects from the BCI competition data sets. The prototype performs a fast classification within time delay of 0.399 second per trial, an accuracy average of 94.47 %, an average transfer rate over all subjects of 20.74 bits/min. The estimated power consumption of the proposed system is around 1.067 Watt (based on an integrated tool-power analysis of Altera corporation).