Abstract
This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34 dB and the IL is less than 2.2 dB at 24-31 GHz. The isolations are better than 27 dB between two double-throw ports and better than 20 dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220 mu m x 140 mu m (with PADs) and its return losses are better than -9 dB at 24-31 GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).