Abstract
In this paper, a low-power high-efficiency inductive link power supply (ILPS) for neural recording and stimulation system-on-chip (SoC) is proposed that delivers 24 mW with 82% power conversion efficiency (PCE). The proposed CMOS power regulator is composed of a self-startup active voltage doubler rectifier (AVD) and a self-biased low dropout regulator (LDO). In addition, a modified low-power self-startup bandgap reference (BGR) circuit is utilized with dual-supply voltages to bias both the LDO circuit and the neural recording and stimulation SoC. The PCE of the AVD is improved through an on-chip calibration comparator for timing control. A prototype of the proposed ILPS is implemented using UMC 0.13 mu m CMOS technology where the active implementation area is 0.06 mm(2). Using 2 V-IN,V-peak at 13.56 MHz, a low-power ILPS is implemented to supply the proposed SoC by 1.2 V and achieve a high-power supply rejection ratio (PSRR) of -20 dB at 20 MHz. Finally, the overall quiescent current of the proposed ILPS from the AVD output and the low dropout regulator (LDO) output equal 7.5 mu A and 8.5 mu A, respectively.