Abstract
Due to the number of functionalities built on the system development, a mixed hardware software systems has increased. To solve the problem of the cost, the flexibility, the time-to-market and the resulting behaviors, many verification methods are used in the literature. This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a SystemC simulator and an FPGA accelerator. Between the SystemC simulator [1,2] and the FPGA hardware platform, a simulation/emulation engine based on different synchronization scheme was established to accelerate the verification and to control the context switch. This work presents an extension for CODIS tool and it enables not only an easy and a high verification speed, with a low cost, but also it presents the real behavior of hardware/software.