Abstract
In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 A to 100 mA consuming quiescent current of 20.5 mu A and 95 mu A, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43 at low load (10 A) to 74 at high load (100 mA) and power supply rejection ratio (PSRR) less than 20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm(2). Post layout simulations show better performance compared with other reported techniques. (C) 2018 Elsevier GmbH. All rights reserved.