Abstract
VLSI architectures for computing higher-order cumulants have gained considerable attention recently, as a consequence of the increasingly evident importance of using cumulant functions as an effective signal processing tool. This paper presents a new approach for designing linear systolic arrays for computing third-order cumulants. First, the estimation of third-order cumulants is formulated elegantly as a sequence of matrix multiplication operations. Then a special structure systolic array for this matrix multiplication is developed. The resulting structure is an efficient unidirectional array which not only is adequate for VLSI implementations but also is suitable for supporting fault-tolerance techniques.