Abstract
In this paper, a study of the existing SRAM (Static Random Access Memory) cell topologies using various FET (Field Effect Transistor) low power devices has been done. Various low power based SRAM cells have been reviewed on the basis of different topologies, technology nodes, and techniques implemented. The analysis of MOSFET(Metal Oxide Semiconductor Field Effect Transistor), FinFET( Fin Field Effect Transistor), CNTFET (Carbon Nano Tube Field Effect Transistor), and TFET (Tunnel Field Effect Transistor) based SRAM cells on the basis of parameters such as stability, leakage current, power dissipation, read/write noise margin, access time has been done. HSPICE, TCAD, Synopsys Taurus, and Cadence Virtuoso were some of the software used for simulation. The simulations were done from a few mu ms to 7nm technology nodes by different authors.