Abstract
An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherland's Micropipelines [1]. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual properties such as nondeterministic (but bounded) prefetch depth beyond a branch instruction, a data dependent throughput, and employs a novel register locking mechanism. This work demonstrates the feasibility of building complex asynchronous systems and gives an indication of the costs and benefits of the Micropipeline approach.