Abstract
Channel Equalization plays an important role in reducing distortion and Inter-Symbol Interference (ISI) to improve the quality of transmission in Ultra-Wide Band (UWB) channel. Many equalization techniques have been proposed in the past but the proposed techniques in this paper describes Infinite Impulse Response (IIR) equalizer architecture which halves the memory requirement of conventional IIR equalizers. This is achieved by exploiting the aperiodically repeated clusters of negative-exponentially decaying segments of Channel Impulse Response (CIR) and hence by providing a single delay-line between the input and output of the equalizer. Further this architecture is realized by implementing on Application Specific Integrated Circuit (ASIC) using Mentor Graphics IC Design tools. Mathematical modeling gives suitable parameters of the IIR Filter, followed by Register Transfer Level (RTL) Design using Very High Descriptive Language (VHDL), ASIC synthesis to TSMC 0.35um process technology, physical modeling using advanced layout techniques. The IIR equalization filter is designed using 8758 Metal Oxide Semi-conductor (MOS) transistors with core cell area of 0.406mm2.