Abstract
Parasitic inductance of global interconnects has gained much attention in the recent past since the inductance can no longer be neglected due to different design and fabrication issues. This has led to a paradigm shift from RC to RLC modeling of global interconnects in modern integrated circuits. However, the extraction of inductance is often expensive and presents a bottleneck in performing RLC analysis of interconnects. Unlike capacitance, the frequency dependence of current distribution through return paths present a major challenge in inductance extraction. In this paper, an efficient analytical model of frequency dependent self-inductance that can be applied to model a wide range of real design scenarios was presented. The model is based on the determination of the inductances at low and very high frequencies, an intermediate frequency point and the corresponding slope of the inductance frequency response. It is demonstrate that the approach is computationally efficient and it produces accurate values of frequency dependent inductance. It is also investigate how the frequency dependence of loop self-inductance affects the RLC delay and show that the pessimism in RLC propagation delay estimation could be as high as 49% if the frequency dependence of inductance is not considered properly. Thus, realistic ( less pessimistic) delay values can be obtained using our model, leading to improved system performance.