Abstract
The Advanced Encryption Standard cryptographic algorithm, named AES, is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange. One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data. Until now, a several AES fault detection schemes against fault injection attacks have been proposed. In this paper, so as to ensure a high level of security against fault injection attacks, a new efficient fault detection scheme based on the AES architecture modification has been proposed. For this reason, the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them. The proposed scheme is independent of the procedure the AES is implemented. Thus, it can be implemented to secure the pipeline and iterative architectures. To evaluate the robustness of the proposed fault detection scheme against fault injection attacks, we conduct a transient and permanent fault attacks and then we determine the fault detection capability; it is about 99.88585% and 99.9069% for transient and permanent faults respectively. We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation. The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.