Abstract
Nowadays, as we are moving towards the Exascale era, the topology-aware process mapping is becoming an important approach to improve the performance and reduce the power consumption of Exascale applications. Accordingly, most researchers in this area have proposed many techniques and approaches for finding the best and efficient topology aware process mapping. In this paper, we have proposed the main modules for any high-performance computing (HPC) topologies mapping technique which includes parallel application behavior analyzer module, physical topology generator module for the target machine, virtual topology generator module for the entire parallel application and topologies mapper module for mapping the process to the processor during runtime. All models work as a dynamic modules.