Abstract
With the augmentation in multimedia technology, demand for high-speed real-time image compression system has also increased. JPEG 2000 is the latest generation of static image coding algorithm which builds and improves on its predecessor JPEG. In JPEG 2000, the embedded block coding with optimal truncation is the core of entropy coding algorithm and the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. Various applications, such as medical imaging, satellite imagery, digital cinema, and others, require high-speed, high-performance BPC architecture. Hardware requirement of these existing architectures is very high, and throughput is low. To solve this problem, an efficient bit plane coder (BPC) architecture has been proposed in which three coding passes operate in parallel and are allowed to progress independently to scan the four bits of each column in parallel. The entire design of BPC encoder is tested on the field-programmable gate array platform. The implementation results show on the one hand that throughput of the proposed architecture of BPC architecture operates at 434.59 MHz. On the other hand, our design outperforms well-known techniques with respect to the processing time, such that it is capable of encoding one bit plane in 232 clock cycles under any circumstances. It can reach 90% reduction when compared to bit plane sequential. Moreover, it is capable of encoding digital cinema size (2048 x 1080) at 42 frames per second. Therefore, it satisfies the requirement of applications like cartography, medical imaging, satellite imagery, and others, which demand high-speed real-time image compression system.