Abstract
Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L
G
reduces to 25 nm for the 65 nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f
T
and f
max
to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its f
T
was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted f
max
in SG SOI was higher (∼40%) compared to DGSOI due to its lower capacitance.