Abstract
This work is facilitating for the improvement of performance of double gate (DG) and single gate (SG) Silicon-on-Insulator (SOI) MOSFETs using high-k (nitride) dielectric stack on source/drain (S/D) extension region (spacer). The results from 2D-ATLAS device simulator show that
high-k dielectric spacer reduces the short-channel effects such as Drain Induced Barrier Lowering (DIBL), Subthreshold slope (S.S) due to eminent vertical fringing electric field. The high-k dielectric spacer ameliorate the Ion/Ioff, transconductance,
gm and voltage gain, Av of the DG and SG-SOI MOSFETs compared to the same devices with conventional spacer. Further more analog/RF performance simulation results reveal an improvement of Av by ≈52% and ≈60%, an increase of ≈20%
and ≈40% in the case of cut-off frequency fT, an increase of ≈19.23% and ≈25% in the case of maximum frequency of oscillation fMAX values of DG and SG-MOSFETs, respectively, with high-k spacer compared to conventional spacer. The results suggest
that DG-SOI MOSFETs with high-k spacer can be available option (because of superior fT and fMAX, which are due to higher gm and lower output conductance, gds) for using high-frequency analog circuits applications
such as Low Noise Amplifier (LNA) and Mixer.