Abstract
Due to high-speed and low area, domino circuits are used in a variety of applications such as comparator, adder, MUX, memory, microprocessor, and adder. In this paper, we propose a keeper controlling network to improve the noise immunity and performance for wide fan-in OR footless domino circuit. In the proposed design, the keeper controlling network controls the keeper transistor. The network itself consists of an NMOS transistor, which acts as a switch and inverter chain. This network turns OFF the keeper transistor at the start of evaluation phase to enhance the speed of the domino circuit. Similarly, it turns ON the keeper transistor, when all inputs are at low voltage in the evaluation phase to enhance the noise immunity. We simulate the proposed design and other existing circuits using 90nm CMOS technology on HSPICE. The simulation results show that the proposed design considerably reduces delay, power consumption, power delay product, and improves unity noise gain as compared to the HS-domino circuit for 32-inputs OR gate.