Abstract
Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of RF circuits. This paper presents an analytical method to assess the performance changes of a CMOS low-noise amplifier (LNA) which incorporates ESD protection, when gate and source inductors
and
are optimally designed. Using a single capacitor model for diode ESD and an accurate MOS device model, a detailed analysis of the LNA design is presented. It has been confirmed analytically that the major changes in the characteristics of an LNA when connected with ESD protection is in input impedance and forward gain. Using a 0.25 µm UMC process parameter, ESD diode capacitance
was calculated. By knowing the diode capacitance, a simple analytical procedure is given to determine series inductances
and
, which will provide optimal 50 Ω input impedance at the operating frequency of 2.4 GHz. Using these values of
,
, and
, a common source CMOS LNA has been designed and fabricated in the 0.25 µm CMOS process. An optimum device size is used to minimize noise figure. Excellent agreement between simulation and measurement for all four
-parameters of the LNA from 2.3 to 2.5 GHz has been achieved with a 2.1 dB minimum noise figure, for power consumption of 13.25 mW.