Abstract
The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the FPGA implementation of this standard are proposed in this work. We propose a reconfigurable SHA-2 processor in the sense that it performs the two hash functions (256, and 512) of the SHA-2 standard for extended signature authentication. This paper investigates optimizations techniques that have recently been proposed in the literature. These techniques consist mostly in operation rescheduling and hardware reutilization, allowing a significant reduction of the critical path while the required area also decreases. As several 64-bit adders are needed in SHA-512 hash value computation, investigations on the adders implementations on FPGAs are analyzed and developed, with a view to reduce the chip area. The proposed processor is compared with the implementation of each hash function in a separate FPGA device to demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware. Two types of FPGAs are evaluated in order to produce realistic results. Speed/area results from this processor are analyzed and are shown to demonstrate that our designs achieves a favorably performances with other FPGA-based implementations. A fastest data throughput is achieved by our optimized design.