Abstract
Dynamic voltage scaling (DVS) is one of the most effective ways to reduce integrated circuit power. However, the programmability of field programmable gate arrays (FPGAs) means that the critical paths depend on the application configured into the FPGA and this makes DVS more difficult. We propose a DVS technique that is able to determine the minimum safe {V_{\text {dd}}} of any application for each FPGA chip. For each application, we create multiple calibration bit-streams that are used to generate a calibration table (CT), which stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale { V_{\text {dd}}} while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a fast-robust-calibration of the FPGA to any application using it. FRoC makes the calibration process invisible to FPGA users, does not add any extra manual steps to the design process, and uses novel algorithms to minimize the extra flash storage requirements for calibration. Our results show that across a large suite of benchmarks the calibration process requires a geomean of less than four bit-streams and our DVS technique achieves a 33% total power reduction on two large applications.