Abstract
Asynchronous VLSI programming provides a flexible abstract formalism for concurrent systems but the is an issue for industrial adoption. The asynchronous design paradigm provides 'elasticity' enabling the system to tolerate delays in communication and computation but can impose a prohibitive communication overhead when applied at a fine-grained level. This paper proposes 'De-elastisation' in a CAD flow for asynchronous dataflow networks to improve the circuits' performance and area. To preserve the architectural advantages of asynchronous design (e.g. short cycles), circuits are classified into blocking and non-blocking loops which the De-elastisation scheme relies upon. The technique is incorporated in the Teak CAD flow. Experimental results on substantial case studies show significant performance and area improvements. This work shows 3 improvement for the first category of circuits, suitable for iterative realisations and DSP-like architectures and 4 for the second category which are suitable for concurrent realisations.