Abstract
International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20
nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60
nm [
<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123–R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15
nm template line width and 10
nm pitch length through out the entire 200
mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46–55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.