Abstract
Longest and average distances and longest delays vs. OCIN topology.
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► We design low latency and diameter on-chip interconnection networks for embedded systems. ► We derive and compare various attributes for 13 64-core interconnection networks. ► We introduce a worst-case network delay computation method based on published wire/router delays. ► Versions of the Enhanced Kite and Spidergon–Donut networks stand out.
On-chip interconnection networks (OCINs) in many-core embedded systems consume large portions of the chip’s area, cost, delay and power. In addition to competing in area, cost, and power, OCINs must feature low diameters to meet real time deadlines. To achieve these goals, designing low-latency networks and sharing network resources are essential. We explore 13 OCINs – some are new such as the Enhanced Kite and the Spidergon–Donut networks – in 64-core systems with various topologies and properties. We also derive and compare their worst case delays, longest and average distances, critical link lengths, bisection bandwidths, total link and router costs, and total arbiter powers. Results indicate that the Enhanced Kite, Kite, Spidergon–Donut and Spidergon–Donut4 stand out in best worst-case delays with the Spidergon–Donut4 additionally featuring lower link and router costs, total arbiter power, and better 2D implementation and scalability.