Abstract
During the reading process of one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier. The net result is that the higher voltage will rise to VDD while the lower one will decrease to 0 V. Simulation results for the 0.13 mm CMOS technology with VDD = 1.2 V reveal that approximately 40% of the read access time is associated with the sense amplifier operation in addition to the area required by each sense amplifier for each column in the memory array. In this paper, a novel readout technique for use with DRAM cells will be presented. This method depends on using an initially charged capacitance, then deciding whether to keep it charged or discharge it according to the stored data. Simulation results show that approximately 20% of the read access time is saved for the case of "1"storage which represents the worst case. The average power of the conventional scheme in case of stored "1"or "0"is 18.5 mW. The corresponding values for the proposed scheme are 9.8 mW and 2.25 mW. The significant reduction of the power consumption can be attributed to the reduction of the voltage swing of the bitline parasitic capacitance and taking the output data at a much smaller capacitance. The powerdelay products (PDPs) for the conventional and proposed readout schemes assuming the worst case (stored "1") are 388.5 fJ and 166.6 fJ, respectively.