Abstract
Any designer wants to perform performance analysis to calculate and exploit performance, in this paper, the main aim is to compute end-to-end delay which also known as "latency" at beginning phase before start working on the implementation to ensure that the proposed design is efficient. This analysis is especially needed in real-time embedded systems and considered to be crucial. Herein, an implemented model, framework, is used to link between a Finite State Machine and a Mathematical Analytical method to compute the expected average end-to-end delay for different layers of abstractions on any network topology using a network simulator. A Hierarchical Generic FSM "HGFSM" was developed earlier to estimate the desired performance metric which is represented by the end-to-end latency in this paper. Several modifications and adjustments were made to the HGFSM and the mathematical model to be suitable for this research. Cisco Packet Tracer ver. 7.3 was used in this paper to show how that performance metric, which is latency, was computed using the implemented framework. In addition, MATLAB was used as a simulator tool along with Cisco Packet Tracer to show the effectiveness of using that framework in finding the desired metric.