Abstract
This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2(m)) based on a previously modified extended Euclidean algorithm. This structure is suitable for fixed size processor that only reuse the core and does not require to modulate the core size when m modified. This structure is extracted by applying a nonlinear methodology that gives the designer more flexibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported efficient designs show that the proposed scalable structure achieves a significant reduction in the area ranging from 83.0% to 88.3% and also achieves a significant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identification (RFID) devices.