Abstract
This brief presents a novel low-complexity scalable serial architecture for finite field multiplication over GF(2(m)) based on irreducible trinomial. This architecture was explored by applying nonlinear technique that allows the designer, using progressive product reduction technique, to control the workload per processor and also allows the communication overhead between processors to be reduced. By comparing the ASIC implementation of the proposed structure to some of the previously published structures, the proposed structure have at least 71.7% lower area and at least 89.9% lower power compared with most of them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in resource constrained applications, such as smart cards, handheld devices, and implantable medical devices.