Abstract
As process technology continues to scale into the nanoscale regime and the overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in determining VLSI system performance. In this paper, we develop an adaptive wavelet interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying an inexpensive Haar wavelet and performing irregular sampling in the frequency domain. The results indicate that our method provides greater accuracy than multi-shift Krylov subspace methods with uniform interpolation points.