Abstract
The PbS/SiO2/Si structures show a clockwise hysteresis of capacitance-voltage (C-V) characteristics. The loop width increases with temperature and sweep time. The conductance-voltage (G-V) characteristics also present a hysteresis effect with two bumps. Both characteristics show a strong shift with frequency. We show that these effects are determined by the positive mobile ions injected in the oxide region during the chemical bath deposition of PbS and by the high concentration Of Si/SiO2 interface states. The corresponding C-V and G-V characteristics are simulated and the main peculiarities of the experimental results are well reproduced by the modeled curves.