Abstract
Digital computation using reversible logic has gained significant research interest in recent years. It promises energy-efficient digital systems due to its information lossless characteristics. A thorough physical design of computationally intensive circuits is essential to analyze the true potential of this developing paradigm. This paper presents a reversible logic implementation of the Fast Fourier Transform (FFT) algorithm as a relevant design case. The proposed architecture’s hierarchical design is based on a reversible standard cell approach. CMOS 0.35μm technology is used for the pass transistor design as well as the full custom layout. Post layout simulations and technology design rule checks are used to validate all design units. The reversible design of an 8-point FFT with 8-bit quantization occupies 0.768 mm2 area and consumes 6.5 mW power at 10 MHz frequency and 3.3 V supply voltage. The major functional units of proposed FFT architecture demonstrate a considerable power saving as compared to their various existing implementations.