Abstract
In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption.
In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires.
The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.