Abstract
The continuous miniaturization of field effect transistors (FETs) dictated by Moore's law has enabled continuous enhancement of their performance during the last four decades, allowing the fabrication of more powerful electronic products (e.g., computers and phones). However, as the size of FETs currently approaches interatomic distances, a general performance stagnation is expected, and new strategies to continue the performance enhancement trend are being thoroughly investigated. Among them, the use of 2D semiconducting materials as channels in FETs has raised a lot of interest in both academia and industry. However, after 15 years of intense research on 2D materials, there remain important limitations preventing their integration in solid-state microelectronic devices. In this work, the main methods developed to fabricate FETs with 2D semiconducting channels are presented, and their scalability and compatibility with the requirements imposed by the semiconductor industry are discussed. The key factors that determine the performance of FETs with 2D semiconducting channels are carefully analyzed, and some recommendations to engineer them are proposed. This report presents a pathway for the integration of 2D semiconducting materials in FETs, and therefore, it may become a useful guide for materials scientists and engineers working in this field.