Abstract
Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for power electronics applications. We have found that SiC MOSFETs when gate-biased at 150 °C show an increasing charge pumping current over time, suggesting that interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above linear-with-log-time and mimics previously observed threshold voltage instabilities, though a causal relationship has not yet been determined. We found the charge trapping after 104 s of BTS increased at a rate of 1x1011 cm-2/dec for NBTS (-3 MV/cm), 0.7x1011 cm-2/dec for PBTS (3 MV/cm), and 0.3x1011 cm-2/dec when grounded. The observed increase in charge trapping has negative implications for the long term stability and reliability of SiC MOS devices under operating conditions.