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Experimental verification of on-chip CMOS fractional-order capacitor emulators
Journal article   Peer reviewed

Experimental verification of on-chip CMOS fractional-order capacitor emulators

G Tsirimokou, C Psychalinos, A.S Elwakil and K.N Salama
Electronics letters, Vol.52(15), pp.1298-1300
21/07/2016
DOI: https://doi.org/10.1049/el.2016.1457

Abstract

Circuits and systems
The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS.

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