Abstract
We present fault-tolerant designs in the form of P-k(j)-graphs and C(k)(j-)graphs, in which n processing units are interlinked as parts of a triangular lattice network, and l of these n units, forming a chain or cycle of maximal length, are used to solve some task. These graphs can tolerate the failure of up to two components or communication links, keeping constant performance. We extend the results to triangular lattices on the torus and Mobius strip.