Abstract
Digital integrated circuits represent a driving force in the evolution of high-performance computing and communication required for the implementation of 5G technology. The architecturally demanding nature of scaling down to ever more compact device dimensions has resulted in an increase in logic gate densities up to billions per millimeter square. Given this evolving complexity, formal verification techniques in modern digital very-large-scale integration (VLSI) designs now face a tremendously challenging search space explosion problem. Despite advances in design debugging approaches utilizing CAD tools in order to provide clarified diagnostic descriptions of bug locations, there remains a significant lack of research efforts toward efficient automatic correction approaches following bug location detection. Here, we introduce an enhanced auto-correction algorithm for fixing logic bugs of type - gate replacement, extra and missing inverters. The primary endpoints of the enhanced algorithm are reductions of logic fixing time as well as size of the compulsory injected circuit for selection of optimal designs using SAT engines. Therefore, the proposed correction algorithm avoids the trade-off between high performance and full percentage of accuracy by gradually shrinking the search space without negatively impacting the quality of the rectified design. Our findings indicate that the proposed correction algorithm outperforms previously published tools in terms of average size of injected design to about 1.5x using ISCAS’85 and ISCAS’89 benchmarks. In addition, average speed of generation of rectified digital designs is increased to about 60.73x and 4x in comparison to two recent rectification mechanisms.