Abstract
Elliptic curve cryptography (ECC) is widely used as an efficient mechanism to secure private data using public-key protocols. We focus on ECC over five standard prime fields recommended by the National Institute of Standard and Technology (with the corresponding prime sizes of 192, 224, 256, 384, and 521 bits) and propose a novel hardware processor that enables flexible security-performance tradeoffs. To enhance performance, our processor exploits parallelism by pipelining modular arithmetic computations and associated input/output data transfers. To enhance security, modular arithmetic computations and associated data transfers are grouped into atomically executed computational blocks. The flexibility of our processor is achieved through the software-controlled hardware programmability, which allows for different scenarios of computing atomic block sequences. A Xilinx Virtex-6 FPGA implementation of the proposed hardware architecture takes between 0.30 ms (192-bit ECC) and 3.91 ms (521-bit ECC) to perform a typical scalar multiplication, which demonstrates both flexibility and efficiency of our processor.