Abstract
Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR-drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.