Abstract
This paper presents the GHz range frequency characterization of gate-source/drain extension region (also known as underlap design) of gate length L-G 90 nm (effective gate length L-eff = 130 nm) single gate (SG) Silicon-on-Insulator (SOI) MOSFET for low power applications. Using an optimal spacer s (similar to 0.8xL(G), where L-G is gate length), it has been found that the device exhibits intrinsic gain of similar to 25 dB in low-moderate inversion region (V-OD = V-GS - V-TH <= 90 mV, where V-OD, V-GS and V-TH are the overdrive, gate and threshold voltages, respectively) at operating frequency of 20 GHz. An accurate (including non-quasi-static and extrinsic parasitic effects) small-signal model for the optimized device has been presented. The comparison of Y-parameters of 2D ATLAS with overall modeled value (up to 20 GHz) has shown an excellent matching (with an average error of <= 5%), whereas results from quasi-static (QS) predictive technology model (PTM) differ significantly (>20%). Optimized underlap device shows transit time frequency f(T) and maximum frequency of oscillation f(MAX), similar to 108 and similar to 130 GHz respectively, with noise figure (NF) similar to 2.8 dB and exhibits unilateral power gain (ULG) similar to 38 dB (V-OD = 90 mV, drain-to-source current I-DS similar to 0.64 mA and drain-to-source voltage V-DS = 1 V) at 20 GHz. Comparison with limited measured data suggest that simulated results are in well conformity, which suggest the possibility of use of underlap device technology in the design of key blocks such as low noise amplifier LNA and mixer for GHz applications.