Abstract
Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (V-t) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2 interface during forming gas anneal together with low O concentration in the TiN enables low NMOS V-t. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS V-t. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3701165]