Abstract
This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.