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High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications
Journal article   Peer reviewed

High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications

Hossain M. Fahad and Muhammad M. Hussain
IEEE transactions on electron devices, Vol.60(3), pp.1034-1039
01/03/2013
DOI: https://doi.org/10.1109/TED.2013.2243151

Abstract

Engineering Engineering, Electrical & Electronic Physical Sciences Physics Physics, Applied Science & Technology Technology
To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow OFF-state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.

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