Abstract
Multiple-valued logic (MVL) circuits using complementary metal-oxide semiconductor (CMOS) technology have been successfully used in implementing a number of digital signal processing (DSP) applications. Heuristic algorithms using the direct cover (DC) approach have been widely used in synthesising (near) minimal two-level realisation of MVL functions. This article presents three improved DC-based algorithms: weighted direct-cover (WDC), ordered direct-cover (ODC) and fuzzy direct-cover (FDC). In the WDC, a weighted-sum scheme for combining a number of different criteria for minterm and implicant selection was applied. In the ODC, a set of criteria for the selection of appropriate minterm and implicant was applied in a specific order. In the FDC, a fuzzy-based algorithm for minterm and implicant selection was introduced. The proposed heuristic algorithms were tested using two sets of benchmarks. The first consists of 50,000 2-variable 4-valued randomly generated functions and the second consists of 50,000 2-variable 5-valued randomly generated functions. The results obtained using the three heuristic algorithms were compared to those obtained using three existing DC-based techniques. It is shown that the heuristic algorithms outperform existing DC-based approaches in terms of the average number of product terms (a measure of the chip area consumed) required to realise a given MVL function.