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In-Line Tunnel Field Effect Transistor: Drive Current Improvement
Journal article   Open access  Peer reviewed

In-Line Tunnel Field Effect Transistor: Drive Current Improvement

Woojin Park, Amir N. Hanna, Arwa T. Kutbee and Muhammad Mustafa Hussain
IEEE journal of the Electron Devices Society, Vol.6(1), pp.721-725
01/01/2018
DOI: https://doi.org/10.1109/JEDS.2018.2844023

Abstract

Delays in-line tunneling Logic gates MOSFET Semiconductor process modeling Silicon TFET TFETs Tunneling tunneling distance tunneling probability vertical structure
A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the subthreshold swing, and the intrinsic time delay, etc. The drive current of the in-line TFET is enhanced nearly 7× compared to the conventional TFET. It also shows a significantly reduced subthreshold swing of 37.2 mV/dec.
url
https://doi.org/10.1109/JEDS.2018.2844023View
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