Integration of retiming with architectural floorplanning: Timing Closure

Journal article

Peer reviewed

A Tabbara, B Tabbara, R. K Brayton and A. R Newton

Integration (Amsterdam), Vol.29(1), pp.25-43

2000

Abstract

Applied sciences

Design. Technologies. Operation analysis. Testing

Electronics

Exact sciences and technology

Integrated circuits

Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology

Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices

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Title: Integration of retiming with architectural floorplanning
Creators - without role: A Tabbara - Department of Electrical Engineering, University of California, P.O. Box 218, Cory Hall, Berkeley, CA 94720, United States
B Tabbara - Department of Electrical Engineering, University of California, P.O. Box 218, Cory Hall, Berkeley, CA 94720, United States
R. K Brayton - Department of Electrical Engineering, University of California, P.O. Box 218, Cory Hall, Berkeley, CA 94720, United States
A. R Newton - Department of Electrical Engineering, University of California, P.O. Box 218, Cory Hall, Berkeley, CA 94720, United States
Publication Details: Integration (Amsterdam), Vol.29(1), pp.25-43
Publisher: Elsevier Science
Identifiers: 9925049108331
Academic Unit: Prince Mohammad Bin Fahd University
Language: English
Resource Type: Journal article