Abstract
The dc component, which may be caused by different factors in the grid voltage, is one of the disturbances that may severely affect the performance of grid synchronization systems and, therefore, grid-tied power converters. In the phase-locked loop (PLL) and frequency-locked loop (FLL)-based grid synchronization systems, which this article focuses on, some solutions to deal with this challenge have been proposed in the literature. One of the best available solutions is adding dc rejection/estimation loop(s) to a standard PLL and FLL structure. This approach provides an estimation of the dc component and, at the same time, makes the PLL and FLL immune to disturbance effects of the dc component. Despite their implementation simplicity, no linear model for the grid synchronization systems with the dc rejection/estimation capability has yet been presented. The main aim of this article is to fill this research gap. It will be shown that developing such models facilitates the examination and the performance enhancement of the grid synchronization systems under study.